![]() ![]() Harvard architecture allowing program access and data access to be executed simultaneously Interrupts (save PC and PS) : 6 cycles, 16 priority levels Signed 16-bit multiplication : 3 cycles Signed 32-bit multiplication : 5 cycles Built-in multiplier/instruction-level support Reduced overhead when processing branches “1” detection, “0” detection, transition point detection ![]() Instruction support for high level languagesįunction entry and exit instructions, instructions for register multi-load and multi-store Memory-to-memory transfer, bit processing, barrel shift instructions, etc. Instructions suitable for embedded applications.16-bit fixed-length instructions (basic instructions) : 1 instruction per cycle.General-purpose registers : 32-bit × 16.32-bit RISC, load/store architecture, five-stage pipeline. ![]() This series is based on the FR80* family CPU and is implemented as a single chip. ■ DESCRIPTIONThe MB91610 series is a line of Fujitsu Microelectronics microcontrollers based on a 32-bit RISC CPU core that feature a variety of peripheral functions for embedded applications that demand high-performance and high-speed CPU processing. ![]()
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